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LTC2656 Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/C Max Reference FEATURES
n n n n n n n n n n
DESCRIPTION
The LTC(R)2656 is a family of octal 16-/12-bit rail-to-rail DACs with a precision integrated reference. The DACs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic.The LTC2656-L has a full-scale output of 2.5V with the integrated 10ppm/C reference and operates from a single 2.7V to 5.5V supply. The LTC2656-H has a full-scale output of 4.096V with the integrated reference and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the DAC full-scale output to two times the external reference voltage. These DACs communicate via a SPI/MICROWIRETM compatible 4-wire serial interface which operates at clock rates up to 50MHz. The LTC2656 incorporates a power-on reset circuit that is controlled by the PORSEL pin. If PORSEL is tied to GND the DACs reset to zero-scale. If PORSEL is tied to VCC, the DACs reset to mid-scale.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 6891433.
Precision 10ppm/C Max Reference Maximum INL Error: 4LSB at 16 Bits Guaranteed Monotonic over Temperature Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2656-L) Integrated Reference Buffers Ultralow Crosstalk Between DACs(<1nV*s) Power-On-Reset to Zero-Scale/Mid-scale Asynchronous LDAC Update Pin Tiny 20-Lead 4mm x 5mm QFN and 20-Lead Thermally Enhanced TSSOP Packages
APPLICATIONS
n n n n n
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment Automotive
BLOCK DIAGRAM
REFCOMP GND REGISTER REGISTER REGISTER REGISTER REFLO VOUTA DAC A REF VCC DAC H REF 4 REGISTER REGISTER REGISTER REGISTER 3 DAC G REF VOUTG INL (LSB) 2 1 0 -1 DAC F REF VOUTF -2 -3 -4 128 DAC E VOUTE 16384 DAC A DAC B DAC C DAC D 32768 CODE
2656 TA01
REF
INTERNAL REFERENCE REF
REFIN/OUT
VOUTH
INL vs Code
VOUTB
DAC B REF
REGISTER
REGISTER
REGISTER
VOUTC
DAC C REF
REGISTER
DAC E DAC F DAC G DAC H 49152 65535
REGISTER
REGISTER
REGISTER
VOUTD
DAC D
REGISTER
CS/LD CONTROL LOGIC SCK LDAC 32-BIT SHIFT REGISTER DECODE
POWER-ON RESET
PORSEL SDO SDI CLR
2656 BD
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LTC2656 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... -0.3V to 6V CS/LD, SCK, SDI, LDAC, CLR, REFLO .......... -0.3V to 6V VOUTA to VOUTH ................. -0.3V to Min(VCC + 0.3V, 6V) REFIN/OUT, REFCOMP ...... -0.3V to Min(VCC + 0.3V, 6V) PORSEL, SDO ................... -0.3V to Min(VCC + 0.3V, 6V) Operating Temperature Range LTC2656C ................................................ 0C to 70C LTC2656I.............................................. -40C to 85C
Maximum Junction Temperature........................... 150C Storage Temperature Range....................... -65 to 150C Lead Temperature (Soldering, 10 sec) FE Package ....................................................... 300C
PIN CONFIGURATION
REFLO TOP VIEW REFLO VOUTA VOUTB REFCOMP VOUTC VOUTD REFIN/OUT LDAC CS/LD 1 2 3 4 5 6 7 8 9 21 20 GND 19 VCC 18 VOUTH 17 VOUTG 16 VOUTF 15 VOUTE 14 PORSEL 13 CLR 12 SDO 11 SDI VOUTB 1 REFCOMP 2 VOUTC 3 VOUTD 4 REFIN/OUT 5 LDAC 6 7 CS/LD 8 SCK 9 10 SDI SDO 21 TOP VIEW VOUTA GND VCC 16 VOUTH 15 VOUTG 14 VOUTF 13 VOUTE 12 PORSEL 11 CLR
20 19 18 17
SCK 10
FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 38C/W, JC = 10C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
UFD PACKAGE 20-LEAD (4mm 5mm) PLASTIC QFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
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LTC2656 PRODUCT SELECTOR GUIDE
LTC2656 B C UFD -L 16 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = Tape and Reel RESOLUTION 16 = 16-Bit 12 = 12-Bit FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UFD = 20-Lead (4mm x 5mm) Plastic QFN FE = 20-Lead Thermally Enhanced TSSOP TEMPERATURE GRADE C = Commercial Temperature Range (0C to 70C) I = Industrial Temperature Range (-40C to 85C) ELECTRICAL GRADE (OPTIONAL) B = 4LSB Maximum INL (16-Bit) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2656 ORDER INFORMATION
LEAD FREE FINISH LTC2656BCFE-L16#PBF LTC2656BIFE-L16#PBF TAPE AND REEL LTC2656BCFE-L16#TRPBF LTC2656BIFE-L16#TRPBF PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C MAXIMUM INL 4 4 4 4 4 4 4 4 1 1 1 1 1 1 1 1 LTC2656FE-L16 20-Lead Thermally Enhanced TSSOP LTC2656FE-L16 20-Lead Thermally Enhanced TSSOP 20-Lead (4mm x 5mm) Plastic QFN 20-Lead (4mm x 5mm) Plastic QFN
LTC2656BCUFD-L16#PBF LTC2656BCUFD-L16#TRPBF 56L16 LTC2656BIUFD-L16#PBF LTC2656BIUFD-L16#TRPBF 56L16 LTC2656BCFE-H16#PBF LTC2656BIFE-H16#PBF LTC2656BCFE-H16#TRPBF LTC2656BIFE-H16#TRPBF
LTC2656FE-H16 20-Lead Thermally Enhanced TSSOP LTC2656FE-H16 20-Lead Thermally Enhanced TSSOP 20-Lead (4mm x 5mm) Plastic QFN 20-Lead (4mm x 5mm) Plastic QFN
LTC2656BCUFD-H16#PBF LTC2656BCUFD-H16#TRPBF 56H16 LTC2656BIUFD-H16#PBF LTC2656BIUFD-H16#TRPBF 56H16 LTC2656CFE-L12#PBF LTC2656IFE-L12#PBF LTC2656CUFD-L12#PBF LTC2656IUFD-L12#PBF LTC2656CFE-H12#PBF LTC2656IFE-H12#PBF LTC2656CUFD-H12#PBF LTC2656IUFD-H12#PBF LTC2656CFE-L12#TRPBF LTC2656IFE-L12#TRPBF LTC2656CUFD-L12#TRPBF LTC2656IUFD-L12#TRPBF LTC2656CFE-H12#TRPBF LTC2656IFE-H12#TRPBF LTC2656CUFD-H12#TRPBF LTC2656IUFD-H12#TRPBF
LTC2656FE-L12 20-Lead Thermally Enhanced TSSOP LTC2656FE-L12 20-Lead Thermally Enhanced TSSOP 56L12 56L12 20-Lead (4mm x 5mm) Plastic QFN 20-Lead (4mm x 5mm) Plastic QFN
LTC2656FE-H12 20-Lead Thermally Enhanced TSSOP LTC2656FE-H12 20-Lead Thermally Enhanced TSSOP 56H12 56H12 20-Lead (4mm x 5mm) Plastic QFN 20-Lead (4mm x 5mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2656 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity (Note 3) Load Regulation (Note 3) (Note 3) VCC = 5.5V, VREF = 2.5V VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VCC = 3V 10%, Internal Reference, Mid-Scale, -7.5mA IOUT 7.5mA ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient SYMBOL PARAMETER VOUT PSR ROUT DAC Output Span Power Supply Rejection DC Output Impedance CONDITIONS Internal Reference External Reference = VEXTREF VCC 10% VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VCC = 3V 10%, Internal Reference, Mid-Scale, -7.5mA IOUT 7.5mA DC Crosstalk (Note 5) Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VEXTREF = 2.75V Code: Zero Scale, Forcing Output to VCC Code: Full Scale, Forcing Output to GND VCC = 2.7V, VEXTREF = 1.35V Code: Zero Scale, Forcing Output to VCC Code: Full Scale, Forcing Output to GND Reference Reference Output Voltage Reference Temperature Coefficient Reference Line Regulation Reference Short-Circuit Current REFCOMP Pin Short-Circuit Current Reference Load Regulation C-Grade (Note 7) I-Grade (Note 7) VCC 10% VCC = 5.5V, Forcing Output to GND VCC = 5.5V, Forcing Output to GND VCC = 3V 10% or 5V 10%, IOUT = 100A Sourcing
l l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2656B-L16/LTC2656-L12 (internal reference = 1.25V)
CONDITIONS LTC2656-12 MIN TYP MAX 12 12 0.1 0.5 0.5 1 LTC2656B-16 MIN TYP MAX 16 16 0.3 2 0.6 1 1 1 2 0.02 0.1 1 TYP 0 to 2.5 0 to 2 * VEXTREF -80 0.04 0.04 1.5 2 1 20 20 10 10 1.248 1.25 2 2 -80 3 60 40 30 5 200 65 65 40 40 1.252 10 0.15 0.15 MAX 1 4 2 4 3 2 UNITS Bits Bits LSB LSB LSB/mA LSB/mA mV mV V/C %FSR ppm/C UNITS V V dB V V/mA V mA mA mA mA V ppm/C ppm/C dB mA A mV/mA nV/Hz
0.04 0.125 0.06 1 1 2 0.02 0.1 1 MIN 0.25 3 2
VREF = 1.25V (Note 4)
l
ISC
Short-Circuit Output Current (Note 6)
Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1F at f = 1kHz
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LTC2656 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Reference Input Range Reference Input Current Reference Input Capacitance (Note 9) Power Supply VCC ICC Positive Supply Voltage Supply Current (Note 8) For Specified Performance VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off VCC = 3V, Internal Reference On VCC = 3V, Internal Reference Off VCC = 5V
l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2656B-L16/LTC2656-L12 (internal reference = 1.25V)
CONDITIONS External Reference Mode (Note 13)
l l l
MIN 0.5
TYP 0.001 40
MAX VCC/2 1
UNITS V A pF
2.7 3.1 2.7 3.0 2.6
5.5 4.25 3.7 3.8 3.2 3
V mA mA mA mA A
ISHDN Digital I/O VIH VIL VOH VOL ILK CIN tS
Supply Current in Shutdown Mode (Note 8) Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance (Note 9) Settling Time (Note 10) Settling Time for 1LSB Step Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse (Note 11) DAC-to-DAC Crosstalk (Note 12) Multiplying Bandwidth
VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V Load Current = -100A Load Current = 100A VIN = GND to VCC
l l l l l l l l
2.4 2.0 0.8 0.6 VCC - 0.4 0.4 1 8 4.2 8.9 2.2 4.9 1.8 1000
V V V V V V A pF s s s s V/s pF nV*s nV*s kHz nV/Hz nV/Hz VP-P VP-P
AC Performance 0.024% (1LSB at 12 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.0015% (1LSB at 16 Bits)
At Mid-Scale Transition, VCC = 3V Due to Full-Scale Output Change, CREFCOMP = CREFOUT = No Load At f = 1kHz At f = 10kHz 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, Internal Reference
3 2 150 85 80 8 600
en
Output Voltage Noise Density Output Voltage Noise
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LTC2656 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity (Note 3) Load Regulation ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient SYMBOL PARAMETER VOUT PSR ROUT DAC Output Span Power Supply Rejection DC Output Impedance DC Crosstalk (Note 5) CONDITIONS Internal Reference External Reference = VEXTREF VCC 10% VCC = 5V 10%, Internal Reference, Midscale, -15mA IOUT 15mA Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VEXTREF = 2.75V Code: Zero Scale, Forcing Output to VCC Code: Full Scale, Forcing Output to GND
l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2656B-H16/LTC2656-H12 (internal reference = 2.048V)
CONDITIONS LTC2656-12 MIN TYP MAX 12 12 0.1 0.5 0.5 1 LTC2656B-16 MIN TYP MAX 16 16 0.3 2 0.6 1 1 2 0.02 0.1 1 TYP 0 to 4.096 0 to 2 * VEXTREF -80 0.04 1.5 2 1 20 20 2.044 C-Grade (Note 7) I-Grade (Note 7) VCC 10% VCC = 5.5V, Forcing Output to GND VCC = 5.5V, Forcing Output to GND VCC = 5V 10%, IOUT = 100A Sourcing External Reference Mode (Note 13)
l l l l l
UNITS Bits Bits
(Note 3) (Note 3) VCC = 5.5V, VREF = 2.5V VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VREF = 2.048V (Note 4)
l l l l l l
1 4 2 3 2
LSB LSB LSB/mA mV mV V/C %FSR ppm/C
0.04 0.125 1 1 2 0.02 0.1 1 MIN 3 2
MAX
UNITS V V dB
0.15
V V/mA V
ISC
Short-Circuit Output Current (Note 6)
65 65 2.048 2 2 -80 3 60 40 35 5 200 2.052 10
mA mA V ppm/C ppm/C dB mA A mV/mA nV/Hz
Reference Reference Output Voltage Reference Temperature Coefficient Reference Line Regulation Reference Short-Circuit Current REFCOMP Pin Short-Circuit Current Reference Load Regulation Reference Input Range Reference Input Current Reference Input Capacitance (Note 9)
Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1F at f = 1kHz 0.5
VCC/2 0.001 40 1
V A pF
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LTC2656 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Power Supply VCC ICC ISHDN Digital I/O VIH VIL VOH VOL ILK CIN tS Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance (Note 9) Settling Time (Note 10) Settling Time for 1LSB Step Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse (Note 11) DAC-to-DAC Crosstalk (Note 12) Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise At f = 1kHz At f = 10kHz 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, Internal Reference At Mid-Scale Transition, VCC = 5V Due to Full-Scale Output Change, CREFCOMP = CREFOUT = No Load 0.024% (1LSB at 12 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.0015% (1LSB at 16 Bits) VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V Load Current = -100A Load Current = 100A VIN = GND to VCC
l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2656B-H16/LTC2656-H12 (internal reference = 2.048V)
CONDITIONS For Specified Performance VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off VCC = 5V
l l l l
MIN 4.5
TYP
MAX 5.5
UNITS V mA mA A
Positive Supply Voltage Supply Current (Note 8) Supply Current in Shutdown Mode (Note 8)
3.3 3.0
4.25 3.7 3
2.4 0.8 VCC - 0.4 0.4 1 8 4.6 7.9 2.0 3.8 1.8 1000 6 3 150 85 80 12 650
V V V V A pF s s s s V/s pF nV*s nV*s kHz nV/Hz nV/Hz VP-P VP-P
AC Performance
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LTC2656 ELECTRICAL CHARACTERISTICS
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V VCC = 2.7V to 5.5V
l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTC2656B-L16/LTC2656-L12/LTC2656B-H16/LTC2656-H12 (see Figure 1).
CONDITIONS MIN 4 4 9 9 10 7 7 20 45 20 7 15 200 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
t9 t10 t12 t13
CLR Pulse Width CS/LD High to SCK Positive Edge LDAC Pulse Width CS/LD High to LDAC High or Low Transition SCK Frequency 50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is the lower end code for which no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is defined from code 128 to code 65535. For VREF = 2.5V and N = 12, kL = 8 and linearity is defined from code 8 to code 4,095. Note 4: Inferred from measurement at code 128 (LTC2656-16) or code 8 (LTC2656-12). Note 5: DC crosstalk is measured with VCC = 5V and using internal reference with the measured DAC at mid-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
Note 7: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 8: Digital inputs at 0V or VCC. Note 9: Guaranteed by design and not production tested. Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 11: VCC = 5V, internal reference mode. DAC is stepped 1LSB between half scale and half scale - 1LSB. Load is 2k in parallel with 200pF to GND. Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output of one DAC due to a full-scale change at the output of another DAC. It is measured with VCC = 5V and using internal reference, with the measured DAC at mid-scale. Note 13: Gain error specification may be degraded for reference input voltages less than 1V. See Gain Error vs Reference Input Voltage curve in the Typical Performance Characteristics section.
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LTC2656 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2656-L16 Integral Nonlinearity (INL)
4 3 2 DNL (LSB) INL (LSB) 1 0 -1 -2 -3 -4 128 16384 32768 CODE
2656 G01
TA = 25C unless otherwise noted. INL vs Temperature
4 3 VCC = 3V
Differential Nonlinearity (DNL)
1.0 VCC = 3V
VCC = 3V
0.5 INL (LSB)
2 1 0 -1
INL (POS)
0
INL (NEG)
-0.5
-2 -3
49152
65535
-1.0 128
16384
32768 CODE
49152
65535
2656 G02
-4 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G03
DNL vs Temperature
1.0 VCC = 3V 1.253 1.252 0.5 DNL (LSB) DNL (POS) VREF (V) 0 DNL (NEG) -0.5 1.248 -1.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G04
REFOUT Voltage vs Temperature
VCC = 3V
1.251 1.250 1.249
1.247 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G05
Settling to 1LSB Rising
CS/LD 3V/DIV VOUT 100V/DIV 8.9s VOUT 100V/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2s/DIV
2656 G06
Settling to 1LSB Falling
3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 8.7s
CS/LD 3V/DIV
2s/DIV
2656 G07
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LTC2656 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2656-H16 Integral Nonlinearity (INL)
4 3 2 DNL (LSB) INL (LSB) 1 0 -1 -2 -3 -4 128 16384 32768 CODE
2656 G08
TA = 25C unless otherwise noted. INL vs Temperature
4 3 VCC = 5V
Differential Nonlinearity (DNL)
1.0 VCC = 5V
VCC = 5V
0.5 INL (LSB)
2 1 0 -1 INL (POS) INL (NEG)
0
-0.5
-2 -3
49152
65535
-1.0 128
16384
32768 CODE
49152
65535
2656 G09
-4 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G10
DNL vs Temperature
1.0 VCC = 5V 2.054 2.052 0.5 DNL (LSB) DNL (POS) 0 DNL (NEG) -0.5 2.044 -1.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G11
REFOUT Voltage vs Temperature
VCC = 5V
2.050 VREF (V) 2.048 2.046
2.042 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G12
Settling to 1LSB Rising
CS/LD 5V/DIV
Settling to 1LSB Falling
6.1s VOUT 250V/DIV VOUT 250V/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.096V 7.9s 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2s/DIV
2656 G13
CS/LD 5V/DIV
2s/DIV
2656 G14
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LTC2656 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2656-12 Integral Nonlinearity (INL)
1.0 VCC = 5V VREF = 2.048V 1.0 VCC = 5V VREF = 2.048V
TA = 25C unless otherwise noted. Settling to 1LSB (12 Bit) Rising
CS/LD 5V/DIV 4.6s
Differential Nonlinearity (DNL)
0.5 DNL (LSB) INL (LSB)
0.5
0
0 VOUT 1mV/DIV
-0.5
-0.5
-1.0
8
1024
2048 CODE
3072
4095
2656 G15
-1.0
RL = 2k, CL = 200pF 1/4 SCALE TO 3/4 SCALE STEP AVERAGE OF 2048 EVENTS VCC = 5V, VFS = 4.095V 8 1024 2048 CODE
2656 G16
3072
4095
2s/DIV
2656 G17
LTC2656-16 Load Regulation
10 8 6 4 VOUT (mV) 2 0 -2 -4 -6 -8 -10 -50 -40 -30 -20 -10 0 10 20 30 40 50 IOUT (mA)
2656 G18
Current Limiting
0.20 0.15 0.10 VOUT (V) 0.05 0 VCC = 5V (LTC2656-H) VCC = 3V (LTC2656-L) INTERNAL REF. CODE = MID-SCALE VOUT (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 -0.10 -0.15 -0.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 IOUT (mA)
2656 G19
Headroom at Rails vs Output Current
5V SOURCING
VCC = 5V (LTC2656-H) VCC = 3V (LTC2656-L) INTERNAL REF. CODE = MID-SCALE
3V SOURCING (LTC2656-L)
-0.05
1.0 0.5 0 0 3V SINKING (LTC2656-L) 1 2 3 456 IOUT (mA) 7 5V SINKING 8 9 10
2656 G20
Offset Error vs Temperature
1.00 0.75 ZERO-SCALE ERROR (mV) OFFSET ERROR (mV) 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3656 G21
Zero-Scale Error vs Temperature
3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G22
Gain Error vs Temperature
64 48 GAIN ERROR (LSB) 32 16 0 -16 -32 -48 -64 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2656 G23
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LTC2656 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2656-16 Offset Error vs Reference Input
2.0 1.5 OFFSET ERROR (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0.5 1.5 1.0 2.0 REFERENCE VOLTAGE (V) 2.5
2656 G24
TA = 25C unless otherwise noted. ICC Shutdown vs VCC
450 400 350 300 ICC (nA) 250 200 150 100 50
Gain Error vs Reference Input
64 48 GAIN ERROR (LSBs) 32 16 0 -16 -32 -48 -64 0.5 1.5 1.0 2.0 REFERENCE VOLTAGE (V) 2.5
2656 G25
VCC = 5.5V OFFSET ERROR OF 8 CHANNELS
VCC = 5.5V GAIN ERROR OF 8 CHANNELS
0 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5
2656 G26
Supply Current vs Logic Voltage
4.0 SWEEP SCK, SDI, CS/LD BETWEEN 0V AND VCC VOUT 1V/DIV
Hardware CLR to Mid-Scale
Hardware CLR to Zero-Scale
VCC = 5V VREF = 2.048V CODE = FULL-SCALE
3.6
VOUT 1V/DIV
ICC (mA)
3.2 VCC = 5V (LTC2656-H) 2.8 CLR 5V/DIV VCC = 5V VREF = 2.048V CODE = FULL-SCALE CLR 5V/DIV
2.4
VCC = 3V (LTC2656-L)
2.0
0
1
3 2 LOGIC VOLTAGE (V)
4
5
2656 G27
1s/DIV
2656 G28
1s/DIV
2656 G29
Multiplying Bandwidth
8 6 4 MAGNITUDE (dB) 2 0 -2 -4 -6 -8 -10 -12 1k VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE 10k 100k FREQUENCY (Hz) 1M
2656 G30
Large-Signal Response
CS/LD 5V/DIV
Mid-Scale Glitch Impulse
VOUT 1V/DIV
VOUT 5mV/DIV
VCC = 5V, 6nV*s TYP (LTC2656-H16)
VCC = 5V VREF = 2.048V ZERO-SCALE TO FULL-SCALE 2.5s/DIV
2656 G31
VOUT 5mV/DIV
VCC = 3V, 3nV*s TYP (LTC2656-L16)
2s/DIV
2656 G32
2656f
13
LTC2656 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2656 DAC-to-DAC Crosstalk (Dynamic)
ONE DAC SWITCH 0-FS 2V/DIV LTC2656-H16, VCC = 5V, 3nV*s TYP CREFCOMP = CREFOUT = NO LOAD VOUT 2mV/DIV LTC2656-H16, VCC = 5V, <1nV*s TYP CREFCOMP = CREFOUT = 0.1F VOUT 2mV/DIV 2s/DIV
2656 G32
TA = 25C unless otherwise noted.
Power-On Reset Glitch
Power-On Reset to Mid-Scale
LTC2656-H
VCC 2V/DIV
VCC 2V/DIV
VOUT 10mV/DIV
ZERO-SCALE
VOUT 1V/DIV
200s/DIV
2656 G34
250s/DIV
2656 G35
Noise Voltage vs Frequency
1200 1000 NOISE VOLTAGE (nV/Hz) 800 600 400 LTC2656-H 200 0 1 LTC2656-L 10 100 1k 10k FREQUENCY (Hz) 100k 1M 5V/DIV VCC = 5V CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1F
0.1Hz to 10Hz Voltage Noise
VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1F
Reference 0.1Hz to 10Hz Voltage Noise
VREFOUT = 1.25V CREFCOMP = CREFOUT = 0.1F
2V/DIV
1 SEC/DIV
2656 G37
1 SEC/DIV
2656 G38
2656 G36
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14
LTC2656 PIN FUNCTIONS
(TSSOP/QFN)
REFLO (Pin 1/Pin 19): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. REFLO should be tied to GND. VOUTA to VOUTH (Pins 2, 3, 5, 6, 15, 16, 17, 18/Pins 20, 1, 3, 4, 13, 14, 15, 16): DAC Analog Voltage Outputs. The output range is 0V to 2 times the voltage at the REFIN/OUT pin. REFCOMP (Pin 4/Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1F capacitor to GND. Connect REFCOMP to GND to allow the use of external reference at start-up. REFIN/OUT (Pin 7/Pin 5): This pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. When acting as an output, the nominal voltage at this pin is 1.25V for L options and 2.048V for H options. For low noise and reference stability tie a capacitor from this pin to GND. This capacitor value must be CREFCOMP , where CREFCOMP is the capacitance tied to the REFCOMP pin. In external reference mode, the allowable reference input voltage range is 0.5V to VCC/2. LDAC (Pin 8/Pin 6): Asynchronous DAC Update Pin. If CS/LD is high, a falling edge on LDAC immediately updates the DAC register with the contents of the input register (similar to a software update). If CS/LD is low when LDAC goes low, the DAC register is updated after CS/LD returns high. A low on the LDAC pin powers up the DAC outputs. All the software power-down commands are ignored if LDAC is low when CS/LD goes high. CS/LD (Pin 9/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed.
SCK (Pin 10/Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 11/Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK (Pin 10). The LTC2656 accepts input word lengths of either 24 or 32 bits. SDO (Pin 12/Pin 10): Serial Interface Data Output. This pin is used for daisy-chain operation. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is continuously driven and does not go high impedance when CS/LD is taken active high. CLR (Pin 13/Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V if the PORSEL pin is tied to GND. If the PORSEL pin is tied to VCC, a logic low at CLR sets all registers to mid-scale code and causes the DAC voltage outputs to go to mid-scale. PORSEL (Pin 14/Pin 12): Power-On Reset Select Pin. If tied to GND, the DAC resets to zero-scale at power-up. If tied to VCC, the DAC resets to mid-scale at power-up. VCC (Pin 19/Pin 17): Supply Voltage Input. For -L options, 2.7V VCC 5.5V and for -H options, 4.5V VCC 5.5V. GND (Pin 20/Pin 18): Ground. Exposed Pad (Pin 21/Pin 21): Ground. Must be soldered to PCB Ground.
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15
LTC2656 BLOCK DIAGRAM
REFCOMP GND REGISTER REGISTER REGISTER REGISTER REFLO VOUTA DAC A REF VCC DAC H REF VOUTH REF INTERNAL REFERENCE REF REFIN/OUT
REGISTER
REGISTER
REGISTER
VOUTB
REGISTER
DAC B REF
DAC G REF
VOUTG
REGISTER
REGISTER
REGISTER
VOUTC
DAC C REF
REGISTER
DAC F REF
VOUTF
REGISTER
REGISTER
REGISTER
VOUTD
REGISTER
DAC D
DAC E
VOUTE
CS/LD CONTROL LOGIC SCK LDAC 32-BIT SHIFT REGISTER DECODE
POWER-ON RESET
PORSEL SDO SDI CLR
2656 BD
TIMING DIAGRAMS
t1 t2 SCK 1 t3 2 t4 3 23 t6 24 t10 SDI t5 CS/LD t8 SDO t13 LDAC t12 t7
Figure 1a
CS/LD t13 LDAC
2656 F01b
2656 F01a
Figure 1b
2656f
16
LTC2656 OPERATION
The LTC2656 is a family of octal voltage output DACs in 20-lead 4mm x 5mm QFN and in 20-lead thermally enhanced TSSOP packages. Each DAC can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. Four combinations of accuracy (16-bit and 12-bit), and full-scale voltage (2.5V or 4.096V) are available. The LTC2656 is controlled using a 4-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2656-L/ LTC2656-H clear the output to zero scale if the PORSEL pin is tied to GND, when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up and may be sensitive to nonzero outputs from the DAC during this time. The LTC2656 contains circuitry to reduce the power-on glitch. The analog outputs typically rise less than 10mV above zero scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics. Alternatively, if the PORSEL pin is tied to VCC, the LTC2656-L/ LTC2656-H sets the output to mid-scale when power is first applied. Power Supply Sequencing and Start-Up For the LTC2656 family of parts, the internal reference is powered up at start-up by default. If an external reference is to be used, the REFCOMP pin must be hardwired to GND. Having REFCOMP hardwired to GND at power up will cause the REFIN/OUT pin to become high impedance and will allow for the use of an external reference at startup. However in this configuration, the internal reference will still be on even though it is disconnected from the REFIN/OUT pin and will draw supply current. In order to use external reference after power-up, the command Select External Reference (0111b) should be used to turn the internal reference off (see Table 1.) The voltage at REFIN/OUT should be kept within the range - 0.3V REFIN/OUT VCC + 0.3V if the external reference is to be used (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is: k VOUT(IDEAL) = * 2 * VREF - VREFLO + VREFLO 2N
(
)
where k is the decimal equivalent of the binary DAC input code, N is the resolution of the DAC, and VREF is the voltage at the REFIN/OUT pin. The resulting DAC output span is 0V to 2 * VREF , as it is necessary to tie REFLO to GND. VREF is nominally 1.25V for LTC2656-L and 2.048V for LTC2656-H, in internal reference mode.
Table 1. Command and Adress Codes
C3 0 0 0 0 0 0 0 0 1 COMMAND* C2 C1 C0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
1 1 1 ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs *Command and address codes not shown are reserved and should not be used.
Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) n Power Down n Power Down Chip (All DACs and Reference) Select Internal Reference (Power-Up Reference) Select External Reference (Power-Down Reference) No Operation
Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges.
2656f
17
LTC2656 OPERATION
The 4-bit command, C3-C0, is loaded first; followed by the 4-bit DAC address, A3-A0; and finally the 16-bit data word. For the LTC2656-16 the data word comprises the 16-bit input code, ordered MSB-to-LSB. For the LTC2656-12 the data word comprizes the 12-bit input code, ordered MSBto-LSB, followed by four don't care bits. Data can only be transferred to the LTC2656 when the CS/LD signal is low. The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits must be transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. The 32-bit word is required for daisy-chain operation, and is also available to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). The 16-bit data word is ignored for all commands that do not include a write operation. Daisy-Chain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO pin is continuously driven and does not go high impedance when CS/LD is taken active high. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisy-chain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight DAC outputs are needed. When in power down, the buffer amplifiers, bias circuits and integrated reference circuits are disabled and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 80k resistors. Input- and DAC-register contents are not disturbed during power down. Any channel or combination of DAC channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using power-down chip command 0101b. For all power-down commands the 16-bit data word is ignored. Normal operation resumes by executing any command which includes a DAC update, in software as shown in Table 1 or by taking the asynchronous LDAC pin low. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay time is 12s. If, on the other hand, all eight DACs and the integrated reference
2656f
18
CS/LD 3 4 7 13 14 17 D7
2656 F02a
SCK 5 6 8 9 10 21 D3 D2 D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 16 20 22 D15 15 19 A0 A2 ADDRESS WORD A1 A3 C0
1
2
OPERATION
SDI
C3
C2
C1
COMMAND WORD
24-BIT INPUT WORD
Figure 2a. LTC2656-16 24-Bit Load Sequence (Minimum Input Word) LTC2656-12 SDI Data Word: 12-Bit Input Code + 4 Don't-Care Bits
CS/LD 6 7 13 14 17 D15 D14 D13 D12 D11 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 A3 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 20 15 19 X 22 D10 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK SDI SDO 17 t3 D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18
CURRENT 32-BIT INPUT WORD
2656 F02b
Figure 2b. LTC2656-16 32-Bit Load Sequence LTC2656-12 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't-Care Bits
LTC2656
19
2656f
LTC2656 OPERATION
are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and integrated reference. In this case, the power-up delay time is 14s. The power up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). However if the reference was powered down using power-down chip command (0101b), then in addition to select internal reference command (0110b), any command that powers up the DACs will also power up the integrated reference. Asynchronous DAC Update Using LDAC In addition to the update commands shown in Table 1, the LDAC pin asynchronously updates all the DAC registers with the contents of the input registers. If CS/LD is high, a low on the LDAC pin causes all the DAC registers to be updated with the contents of the input registers. If CS/LD is low, a low going pulse on the LDAC pin before the rising edge of CS/LD powers up all the DAC outputs but does not cause the output to be updated. If LDAC remains low after the rising edge of CS/LD, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC outputs are updated. The DAC outputs are powered up when LDAC is taken low, independent of the state of CS/LD. The integrated reference is also powered up if it was powered down using power-down chip (0101b) command. The integrated reference will not power up when LDAC is taken low, if it was powered down using select external reference (0111b) command. If LDAC is low at the time CS/LD goes high, it inhibits any software power-down command (power down n, powerdown chip, select external reference) that was specified in the input word. Reference Modes For applications where an accurate external reference is not available, the LTC2656 has a user-selectable, integrated reference. The LTC2656-L has a 1.25V reference that provides a full-scale DAC output of 2.5V. The LTC2656-H has a 2.048V reference that provides a full-scale DAC output of 4.096V. Both references exhibit a typical temperature drift of 2ppm/C. Internal reference mode can be selected by using command 0110b, and is the power-on default. A buffer is needed if the internal reference is required to drive external circuitry. For reference stability and low noise, it is recommended that a 0.1F capacitor be tied between REFCOMP and GND. In this configuration, the internal reference can drive up to 0.1F capacitive load without any stability problems. In order to ensure stable operation, the capacitive load on the REFIN/OUT pin should not exceed the capacitive load on the REFCOMP pin. The DAC can also operate in external reference mode using command 0111b. In this mode, the REFIN/OUT pin acts as an input that sets the DAC's reference voltage. The input is high impedance and does not load the external reference source. The acceptable voltage range at this pin is 0.5V REFIN/OUT VCC/2. The resulting full-scale output voltage is 2 * VREFIN/OUT . For using external reference at start-up, see the Power Supply Sequencing and Start-Up section. Integrated Reference Buffers Each of the eight DACs in LTC2656 has its own integrated high performance reference buffer. The buffers have very high input impedance and do not load the reference voltage source. These buffers shield the reference voltage from glitches caused by DAC switching and thus minimize DACto-DAC dynamic crosstalk. Typically DAC-to-DAC crosstalk is less than 3nV*s. By tying 0.1F capacitors between REFCOMP and GND, and also between REFIN/OUT and GND, this number can be reduced to less than 1nV*s. See the curve DAC-to-DAC Dynamic Crosstalk in the Typical Performance Characteristics section. Voltage Outputs Each of the LTC2656's eight rail-to-rail output amplifiers contained in these parts has a guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of
2656f
20
LTC2656 OPERATION
load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.04 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30 * 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF . Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separate. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be connected to analog ground. The REFLO pin should be connected to the system star ground. Resistance from the REFLO pin to the system star ground should be as low as possible. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit the lowest codes as shown in Figure 3b. Similarly, limiting can occur in external reference mode near full scale when the REFIN/OUT pin is at VCC/2. If VREFIN/OUT = VCC/2 and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC are shown in Figure 3c. No full-scale limiting can occur if VREFIN/OUT (VCC - FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
VREF = VCC POSITIVE FSE
VREF = VCC
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE
2656 F03
(3c)
OUTPUT VOLTAGE 0 32,768 INPUT CODE 65,535
0V NEGATIVE OFFSET INPUT CODE
(3a) (3b)
Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (3a) Overall Transfer Function (3b) Effect of Negative Offset for Codes Near Zero-Scale (3c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
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21
LTC2656 PACKAGE DESCRIPTION
FE Package 20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
3.86 (.152)
6.40 - 6.60* (.252 - .260) 3.86 (.152) 20 1918 17 16 15 14 13 12 11
6.60 0.10 4.50 0.10
SEE NOTE 4
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC
6.40 2.74 (.252) (.108) BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX
0 -8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE20 (CB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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22
LTC2656 PACKAGE DESCRIPTION
UFD Package 20-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 0.05
4.50
0.05 3.10
1.50 REF 0.05
2.65
0.05 3.65 0.05
PACKAGE OUTLINE
0.25 0.05 0.50 BSC 2.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 1.50 REF 19 20 0.40 0.10 PIN 1 NOTCH R = 0.20 OR C = 0.35
1 2 5.00 0.10 (2 SIDES) 2.50 REF 3.65 0.10 2.65 0.10
(UFD20) QFN 0506 REV B
0.200 REF 0.00 - 0.05
R = 0.115 TYP
0.25
0.05
0.50 BSC
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2656f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2656 TYPICAL APPLICATION
Digitally Controlled Output Voltage 1.1A Supply
VCC MID-SCALE ZERO-SCALE C1 0.1F 4 2 JP2 VCC 3 1 C1 0.1F C1 0.1F R4 7.5k CLR VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH 20 1 3 4 13 14 15 16 VIN 1.2V TO 36V IN VCONTROL LT3080
TO MICROCONTROLLER
REFCOMP REFIN/OUT LDAC PORSEL VCC 7 CS 8 SCK 10 SDO 9 LTC2656* SDI
1F SET
+ -
OUT VOUT 2.2F
GND REFLO GND 21 19 18
NOTE: LT3080 MINIMUM LOAD CURRENT IS 0.5mA
2656 TA02
*PIN NUMBERS INDICATED ARE FOR THE QFN PACKAGE
RELATED PARTS
PART NUMBER LTC1660/LTC1665 LTC1664 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2605/LTC2615/ LTC2625 LTC2606/LTC2616/ LTC2626 LTC2609/LTC2619/ LTC2629 LTC2636 LTC2641/LTC2642 LTC2704 LTC2755 DESCRIPTION Octal 10-/8-Bit VOUT DACs in 16-Pin Narrow SSOP Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP Single 16-Bit VOUT DAC with 1LSB INL, DNL Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Octal 16-/14-/12-Bit VOUT DACs with I2C Interface Single 16-/14-/12-Bit VOUT DACs with I2C Interface Quad 16-/14-/12-Bit VOUT DACs with I2C Interface Octal 12-/10-/8-Bit VOUT DACs with 10ppm/C Reference Single 16-/14-/12-Bit VOUT DACs with 1LSB INL, DNL Quad 16-/14-/12-Bit VOUT DACs with 2LSB INL, 1LSB DNL Quad 16-/14-/12-Bit IOUT DACs with 1LSB INL, 1LSB DNL COMMENTS VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Parallel Interface, Precision 16-Bit Settling in 2s for 10V Step 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output 270A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC 125A per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, SPI Interface 1LSB (Max) INL, DNL, 3mm x 3mm DFN and MSOP Packages, 120A Supply Current, SPI Interface Software Programmable Output Ranges Up to 10V, SPI Interface Software Programmable Output Ranges Up to 10V, Parallel Interface
2656f
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0809 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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